An integrated circuit (IC) is an electrical circuit which includes resistors, capacitors, transistors and other well-known electrical components which are typically connected together on a small slice of silicon to form a plurality of gates. The gates in turn are configured to provide addresses, registers, multiplexers and other functional combinations required to perform logical operations.
A correctly manufactured IC includes various input and output leads. In normal operation the input leads receive various input signal combinations and the IC provides output signals as a function of the input signal combinations. A complete set of simultaneous output signals is referred to herein as an output signature.
To test IC integrity, testing procedures have been designed to excite IC gates with input signal combinations, observe output signatures, and compare output signatures to known correct output signatures. IC testing procedures have taken two general forms referred to herein as built-in self-test (BIST) and automatic test equipment (ATE) tests. BIST, as the name implies, incorporates special testing hardware on the IC itself. The most popular form of BIST, is called "SCAN BIST." Many variations of SCAN BIST exist but, in general, they all require among other things, special gates called "scan flip flops," clocking circuitry, and some type of cyclic redundancy check (CRC) generator.
Scan flip flops are capable of assuming both a functional state and a test state. In the functional state, BIST SCAN flip flops operate to perform instructions required by IC applications. In the test state, however, instead of performing required instructions, SCAN flip flops are reconfigured into a single expansive serial scan chain for test purposes.
During a test cycle, all SCAN flip flops are gated into their test state, forming the scan chain. The CRC generator provides pseudo-random test vectors, which are IC input combinations created to excite IC logic. The vectors are provided to the IC and are shifted along the scan chain. Typically, a reduced set of vectors including less than all possible vectors are provided so that most, but not all, of the IC logic is tested during a test cycle. After an entire reduced set of test vectors has been run, a compressed IC output signature (also created by a CRC generator) is read from the IC and compared to an error-free signature. This compressed output signature at the end of a test cycle is deterministic (i.e. is a function of all preceding IC input combinations and should be identical for each correctly built IC). Therefore, when the error free and final or end output signatures are not identical at the end of a test cycle, the IC is faulty.
Where the error free and final output signatures are identical, there is a degree of certainty that the IC was manufactured correctly. The degree of certainty is known as fault coverage, which is equal to the mount of logic in the IC stimulated and observed by the reduced test vector set compared to the total amount of logic in the IC. Typical fault coverage using the SCAN test method is approximately 98%.
While BIST methods provide acceptable fault coverage, they are disadvantageous for at least three reasons. First, BIST methods are relatively expensive because they require the above mentioned specialized on chip hardware, which typically has no function other than testing the IC.
Second, because SCAN flip flops must assume both functional and test states, their configurations are complex when compared to single state gates. Complex flip flop configurations result in slower performance during functional IC operation and, therefore, a lower overall IC speed. Moreover, routing scan chains also adds to test overhead, resulting in a slower chip.
Third, because BIST SCAN requires relatively complex chip hardware, the process of designing a BIST SCAN capable chip is relatively more labor intensive, which adds to overall chip cost.
Some of the problems associated with BIST SCAN methods are eliminated using ATE methods. In ATE methods, test hardware is provided in a testing module which is wholly separate from the IC. The testing module is used repetitively to test thousands of identical ICs. In ATE methods, each IC is placed in a testing module tester interface and IC input leads are stimulated with a plurality of test vectors. In ATE testing methods, output signatures are not compressed as input test vectors are altered. Therefore, test module hardware is required to observe an IC output signature for each test vector.
Here, test vectors are created by an engineer to excite as much IC logic as possible. Each specific vector is aimed at testing a specific section of IC logic and, when applied, causes a deterministic response from the IC. By comparing IC responses to known correct responses, high fault coverage can be achieved.
ATE methods are advantageous because typical single state flip flops (i.e. flip flops capable of operating only in a functional state as opposed to functional and serial chain testing states) are relatively inexpensive, and, therefore, overall IC hardware costs are minimized. In addition, because single state flip flops are used, ATE hardware does not reduce IC speed when performing a functional program. Moreover, ATE methods allow functional testing of IC's without reconfiguration into scan chains.
Unfortunately, ATE methods also have a number of shortcomings. First, ATE test vectors are difficult to generate. Instead of using random inputs generated by a CRC generator as in BIST testing, specific ATE test vectors must be provided to excite IC logic. Second, because of the enormous number of possible test vectors, a large tester module memory is required to store ATE test vectors. Moreover, because ATE output signatures are not compressed, an output signature corresponding to each test vector should be compared to a separate correct signature to provide the greatest fault coverage possible. Therefore, tester module memory also must be provided to store thousands of correct signatures, one for each test vector, for comparison.
Third, ATE testing is slow due to the speed of the signals being tested; sampling times, wire delays, and other tester configuration limitations. Not only is ATE's reduced speed burdensome, but testing speed can have adverse effects on the reliability of tests. Some IC tests only can be meaningfully performed at full IC operating speed. These tests often exceed the capabilities of the most capable and expensive of currently available ATE units.
Fourth, while ATE testing may be somewhat practical when considering testing of general purpose IC's, ATE testing is inherently impractical when dealing with application specific integrated circuits (ASIC's). Recently, the IC industry has developed improved compiler design techniques which allow IC engineers to rapidly customize IC designs for specific applications. Rapid compiler design techniques have fueled a surge of ASICs which are tailored to application specific requirements, thus reducing IC hardware costs associated with standardized ICs. Unfortunately, because each application specific IC type has a unique hardware configuration, their advent has only exacerbated the ATE IC integrity testing task. Because different ASIC types incorporate different hardware configurations, unique sets of test vectors must be generated for each different ASIC type. Because test vectors must be provided by an engineer as opposed to a random generating mechanism, ATE testing of ASIC devices is extremely labor intensive.
Fifth, since ATE has limited access to the internal logic of the chip, it usually has lower fault coverage compared to BIST SCAN.
Therefore, while both BIST and ATE methods can be used to identify IC faults, both methods have disadvantages which have not been addressed by the industry. Therefore, it would be advantageous to have an IC testing method and apparatus which can test IC functions at operating frequencies and in a cost effective manner without requiring massive amounts of excess on-chip hardware or dedicated ATE devices.